| Instruction Processing |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ä | For
programming purposes, each processor |
|||||||||||||||
| is
characterized by its register set and its |
||||||||||||||||
| instruction
set |
||||||||||||||||
| ä | Instructions:
operations and operands |
|||||||||||||||
| ä | How
does a processor architecture work? |
|||||||||||||||
| ä | Von-Neuman
architecture (repeat 3 steps) |
|||||||||||||||
| 1.
Fetch instruction |
||||||||||||||||
| 2.
Decode instruction |
||||||||||||||||
| 3.
Execute instruction |
||||||||||||||||
| ä | Older
processors did this sequentially |
|||||||||||||||
| ä | Newer
processors have pipelines so that steps |
|||||||||||||||
| 1-3
are done in parallel whenever possible |
||||||||||||||||
