© Thomas Kunz 2000
SCE 574
235
    Page Table Implementation
äA set of dedicated registers
äReasonable only for small page tables
äExample:
ä 16 bit logical address space
ä page size = 8K
ä page table size = 8
äMemory
äuse a PTBR to point to the page table of the current process
ä2 memory accesses are needed for every data access
äspeed could be intolerable
äAssociative registers
äAssociative registers or translation look-aside buffers (TLBs)
äOnly few page table entries are kept in the associative registers
äThe hit ratio is the percentage of times that a page number is found in the associative registers