Page Table Implementation
ä A set of dedicated registers
ä Reasonable only for small page tables
ä Example:
     16 bit logical address space
     page size = 8K
     page table size = 8
ä Memory
ä use a PTBR to point to the page table of the current
process
ä 2 memory accesses are needed for every data access
ä speed could be intolerable
ä Associative registers
ä Associative registers or translation look-aside buffers
(TLBs)
ä Only few page table entries are kept in the associative
registers
ä The hit ratio is the percentage of times that a page
number is found in the associative registers